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| Campo DC | Valor | Lengua/Idioma |
|---|---|---|
| dc.contributor.advisor | Velez-Isasmendi, I. (Igone) | - |
| dc.contributor.advisor | Sevillano Berasategui, J. F. (Juan Francisco) | - |
| dc.creator | Tomasena-Arriaga, K. (Koldo) | - |
| dc.date.accessioned | 2013-10-22T07:44:46Z | - |
| dc.date.available | 2013-10-22T07:44:46Z | - |
| dc.date.issued | 2013-10-22 | - |
| dc.date.submitted | 2013-07-12 | - |
| dc.identifier.uri | https://hdl.handle.net/10171/34245 | - |
| dc.description.abstract | An integrated, powerful and flexible development environment has been created in this research work in order to simulate and verify electronic systems starting from a very high abstraction level. The system architecture design, the algorithm tuning and the functional verification can be performed efficiently early in the development process by means the proposed contributions. | es_ES |
| dc.language.iso | eng | es_ES |
| dc.subject | Transaction Level Modeling (TLM). | es_ES |
| dc.subject | Assertion-based Verification (ABV). | es_ES |
| dc.subject | Model-driven Design (MDD). | es_ES |
| dc.subject | Automatic code generation. | es_ES |
| dc.subject | SystemC. | es_ES |
| dc.title | A methodology and framework to assist in the architecture design and functional verification of complex electronic systems. | es_ES |
| dc.type | info:eu-repo/semantics/doctoralThesis | es_ES |
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