González-Jiménez, J.L. (José Luís)

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    A wideband and high-linearity E-band transmitter integrated in a 55-nm SiGe technology for backhaul point-to-point 10-Gb/s links
    (IEEE, 2017-08) Saavedra, C.E. (Carlos E.); Del-Rio-Orduña, D. (David); Berenguer-Pérez, R.J. (Roque José); Tamir, N. (Nataly); Dehos, C. (Cédric); Gurutzeaga-Zubillaga, I. (Iñaki); Velez-Isasmendi, I. (Igone); Rezola-Garciandia, A. (Ainhoa); Sevillano Berasategui, J. F. (Juan Francisco); Siligaris, A. (Alexandre); Gunnarsson, S. E. (Sten E.); González-Jiménez, J.L. (José Luís)
    This paper presents the design of a wideband and high-linearity E-band transmitter integrated in a 55-nm SiGe BiCMOS technology. It consists of a double-balanced bipolar ring mixer which upconverts a 16-21-GHz IF signal to the 71-76- and 81-86-GHz bands by the use of a 55/65-GHz local oscillator signal, followed by a broadband power amplifier which employs 2-way output power combining using an integrated low-loss balun transformer. The transmitter exhibits an average conversion gain of 24 dB and 22 dB at the 71-76- and 81-86-GHz bands, respectively, with an output 1-dB compression point greater than 14 and 11.5 dBm at each band. A maximum output power of 16.8 dBm is measured at 71 GHz. The dc power consumption is 575 mW. The presented transmitter is used to demonstrate the transmission of a 10.12-Gb/s 64 quadrature amplitude modulated signal with a spectral efficiency of 5.06 bit/s/Hz, which makes it suitable for use in future highcapacity backhaul and fronthaul point-to-point links.
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    A 15-21 GHz I/Q upconverter with an on-chip linearization circuit for 10 Gbps mm-wave tinks.
    (IEEE, 2017-05) Del-Rio-Orduña, D. (David); Berenguer-Pérez, R.J. (Roque José); Puyal, V. (Vincent); Gurutzeaga-Zubillaga, I. (Iñaki); Velez-Isasmendi, I. (Igone); Rezola-Garciandia, A. (Ainhoa); Sevillano Berasategui, J. F. (Juan Francisco); González-Jiménez, J.L. (José Luís)
    This letter presents a 15-21 GHz I/ Q upconverter, based on two Gilbert-cell mixers with an on-chip wideband linearization loop that extends the linear region and allows power efficient operation at backoff power levels. A quadrature LO signal is generated using an integrated two-stage polyphase filter. Measurements show a conversion gain of -5.5 dB, an output 1-dB compression point of 0 dBm, and an image suppression of 40 dB over the 6-GHz output bandwidth. An error vector magnitude of 3.5% is obtained for a 10-Gb/s 64-QAM signal with a bandwidth of 2 GHz. The circuit is integrated in a 55-nm BiCMOS process and occupies 1.07 mm(2) . The dc power consumption is 61 mW.