Del-Rio-Orduña, D. (David)
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- A wideband and high-linearity E-band transmitter integrated in a 55-nm SiGe technology for backhaul point-to-point 10-Gb/s links(IEEE, 2017-08) Saavedra, C.E. (Carlos E.); Del-Rio-Orduña, D. (David); Berenguer-Pérez, R.J. (Roque José); Tamir, N. (Nataly); Dehos, C. (Cédric); Gurutzeaga-Zubillaga, I. (Iñaki); Velez-Isasmendi, I. (Igone); Rezola-Garciandia, A. (Ainhoa); Sevillano Berasategui, J. F. (Juan Francisco); Siligaris, A. (Alexandre); Gunnarsson, S. E. (Sten E.); González-Jiménez, J.L. (José Luís)This paper presents the design of a wideband and high-linearity E-band transmitter integrated in a 55-nm SiGe BiCMOS technology. It consists of a double-balanced bipolar ring mixer which upconverts a 16-21-GHz IF signal to the 71-76- and 81-86-GHz bands by the use of a 55/65-GHz local oscillator signal, followed by a broadband power amplifier which employs 2-way output power combining using an integrated low-loss balun transformer. The transmitter exhibits an average conversion gain of 24 dB and 22 dB at the 71-76- and 81-86-GHz bands, respectively, with an output 1-dB compression point greater than 14 and 11.5 dBm at each band. A maximum output power of 16.8 dBm is measured at 71 GHz. The dc power consumption is 575 mW. The presented transmitter is used to demonstrate the transmission of a 10.12-Gb/s 64 quadrature amplitude modulated signal with a spectral efficiency of 5.06 bit/s/Hz, which makes it suitable for use in future highcapacity backhaul and fronthaul point-to-point links.
- A high accuracy 3.1V voltage limiter for enabling high performance RFID sensor applications.(IEEE, 2019) Solar-Ruiz, H. (Hector); Del-Rio-Orduña, D. (David); Berenguer-Pérez, R.J. (Roque José); Beriain, A. (Andoni); Gurutzeaga-Zubillaga, I. (Iñaki); Rezola-Garciandia, A. (Ainhoa)This paper presents a low power voltage limiter design that avoids possible damages in the analog front-end of a RFID sensor due to voltage surges whenever the tag gets close to the reader. The proposed voltage limiter design takes advantage of the implemented bandgap reference block in order to provide a highly accurate limiting voltage in spite of temperature variation and process dispersion. The measured limiting voltage is 3.1V while showing a low current consumption of 100nA when the reader and the tag are far away, so that the sensitivity of the tag is not impacted due to an undesired consumption in the voltage limiter. The circuit is implemented in a low cost 180nm CMOS technology.
- A 21 m operation range RFID tag for "Pick to Light" applications with a photovoltaic harvester(2020) Solar-Ruiz, H. (Hector); Del-Rio-Orduña, D. (David); Berenguer-Pérez, R.J. (Roque José); Lopez-Gasso, A. (Alberto); Golpe, D. (Diego); Beriain, A. (Andoni); Astigarraga, A. (Aingeru)In this paper, a novel Radio-Frequency Identification (RFID) tag for "pick to light" applications is presented. The proposed tag architecture shows the implementation of a novel voltage limiter and a supply voltage (VDD) monitoring circuit to guarantee a correct operation between the tag and the reader for the "pick to light" application. The feasibility to power the tag with different photovoltaic cells is also analyzed, showing the influence of the illuminance level (lx), type of source light (fluorescent, LED or halogen) and type of photovoltaic cell (photodiode or solar cell) on the amount of harvested energy. Measurements show that the photodiodes present a power per unit package area for low illuminance levels (500 lx) of around 0.08 mu W/mm(2), which is slightly higher than the measured one for a solar cell of 0.06 mu W/mm(2). However, solar cells present a more compact design for the same absolute harvested power due to the large number of required photodiodes in parallel. Finally, an RFID tag prototype for "pick to light" applications is implemented, showing an operation range of 3.7 m in fully passive mode. This operation range can be significantly increased to 21 m when the tag is powered by a solar cell with an illuminance level as low as 100 lx and a halogen bulb as source light.
- SDR-based monostatic Chipless RFID Reader with Vector Background Subtraction Capabilities(IEEE, 2023-11) Del-Rio-Orduña, D. (David); Villa-González, F. (Fátima); Bhattcharyya, R. (Rahul); Rezola-Garciandia, A. (Ainhoa); Valderas Gazquez, D.(Daniel)This article presents a high-performance frequency-domain chipless RFID reader with vector background subtraction capabilities, implemented in a software-defined radio (SDR) for the first time. The proposed reader is low-cost, compact size, and versatile. It is implemented in a USRP N210 paired to a modified CBX-40 daughterboard, enabling magnitude and phase data acquisition in a monostatic (one antenna) set up. The reader can perform a vector background subtraction operation between two complex measurements (with and without a chipless tag) to suppress the self-interference (SI) that hinders the response of the tag and provide 40 dB of dynamic range. To demonstrate the performance of the reader, the spectral signatures of three frequency-coded (FC) tags with four resonant frequencies are captured over the 1.5-4-GHz band scanned with 10-MHz resolution in 251 ms, obtaining comparable measurements to those of an expensive laboratory vector network analyzer (VNA) from 20 to 40 cm. The detected resonant frequency offset between both devices is Delta f(r) <= 4.18% . It is also demonstrated that the proposed reader can track a resonant frequency shift and therefore be used in real-time sensing applications.
- Built-in-self-calibration for I/Q imbalance in wideband millimeter-wave gigabit transmitters.(IEEE, 2017-11) Del-Rio-Orduña, D. (David); Berenguer-Pérez, R.J. (Roque José); Gurutzeaga-Zubillaga, I. (Iñaki); Velez-Isasmendi, I. (Igone); Rezola-Garciandia, A. (Ainhoa); Sevillano Berasategui, J. F. (Juan Francisco)This paper addresses the estimation and compensation of I/Q imbalance, one of the most prominent impairments found in wideband zero-intermediate frequency transceivers (TRxs). The I/Q imbalance encountered in this kind of TRx comprises not only frequency-selective gain and phase imbalance but also delay imbalance. Unless appropriate compensation is applied, the I/Q imbalance significantly degrades the performance of a communication system. This paper presents a novel compensation technique for transmitter I/Q imbalance based on built-in-self-calibration, a low cost and robust compensation technique that enables manufacturing as well as in-field calibration with low computational complexity. The method's performance is evaluated in a TRx with 64-quadratic-amplitude modulation and 2 GHz of bandwidth implemented with real hardware. The measurements show that the proposed technique achieves an image rejection ratio greater than 35 dB in the entire 2 GHz bandwidth and an error vector magnitude lower than 3%.
- A 15-21 GHz I/Q upconverter with an on-chip linearization circuit for 10 Gbps mm-wave tinks.(IEEE, 2017-05) Del-Rio-Orduña, D. (David); Berenguer-Pérez, R.J. (Roque José); Puyal, V. (Vincent); Gurutzeaga-Zubillaga, I. (Iñaki); Velez-Isasmendi, I. (Igone); Rezola-Garciandia, A. (Ainhoa); Sevillano Berasategui, J. F. (Juan Francisco); González-Jiménez, J.L. (José Luís)This letter presents a 15-21 GHz I/ Q upconverter, based on two Gilbert-cell mixers with an on-chip wideband linearization loop that extends the linear region and allows power efficient operation at backoff power levels. A quadrature LO signal is generated using an integrated two-stage polyphase filter. Measurements show a conversion gain of -5.5 dB, an output 1-dB compression point of 0 dBm, and an image suppression of 40 dB over the 6-GHz output bandwidth. An error vector magnitude of 3.5% is obtained for a 10-Gb/s 64-QAM signal with a bandwidth of 2 GHz. The circuit is integrated in a 55-nm BiCMOS process and occupies 1.07 mm(2) . The dc power consumption is 61 mW.
- Temperature-dependent I/Q imbalance compensation in ultra-wideband millimeter-wave multi-gigabit transmitters(IEEE, 2020-01) Del-Rio-Orduña, D. (David); Berenguer-Pérez, R.J. (Roque José); Martín, B. (Belén); Gurutzeaga-Zubillaga, I. (Iñaki); Velez-Isasmendi, I. (Igone); Rezola-Garciandia, A. (Ainhoa); Sevillano Berasategui, J. F. (Juan Francisco)Changes in ambient temperature or chip temperature result in variations in the in-phase and quadrature (I/Q) gain and phase imbalance. As a consequence, the overall system performance can be seriously degraded, especially in wideband multi-Gb/s systems, where the I/Q imbalance is highly selective in frequency. Unless appropriately considered, temperature drifts can decrease the image rejection ratio (IRR) of the transmitter. This article presents a novel compensation method for temperature-dependent transmitter I/Q imbalance over the entire temperature range. It consists of a simple predistortion technique that, based on a few factory characterizations of gain and phase imbalance, is able to estimate and correct the I/Q imbalance at any temperature, without interrupting the normal functionality of the system. The proposed method is assessed in a 2-GHz, 64-QAM transceiver implemented with real hardware. The measurements show that the proposed approach is able to keep the IRR greater than 35 dB in the entire bandwidth and an error vector magnitude (EVM) lower than 3 over a temperature range of 70 C.
- SDR-Based monostatic chipless RFID reader with vector backgroud substration capabilities(IEEE, 2023) Del-Rio-Orduña, D. (David); Bhattacharyya, R. (RahuL); Villa-González, F. (Fátima); Rezola-Garciandia, A. (Ainhoa); Valderas Gazquez, D.(Daniel)This article presents a high-performance frequency-domain chipless RFID reader with vector background subtraction capabilities, implemented in a software-defined radio (SDR) for the first time. The proposed reader is low-cost, compact size, and versatile. It is implemented in a USRP N210 paired to a modified CBX-40 daughterboard, enabling magnitude and phase data acquisition in a monostatic (one antenna) set up. The reader can perform a vector background subtraction operation between two complex measurements (with and without a chipless tag) to suppress the self-interference (SI) that hinders the response of the tag and provide 40 dB of dynamic range. To demonstrate the performance of the reader, the spectral signatures of three frequency-coded (FC) tags with four resonant frequencies are captured over the 1.5-4-GHz band scanned with 10-MHz resolution in 251 ms, obtaining comparable measurements to those of an expensive laboratory vector network analyzer (VNA) from 20 to 40 cm. The detected resonant frequency offset between both devices is Delta f(r) <= 4.18% . It is also demonstrated that the proposed reader can track a resonant frequency shift and therefore be used in real-time sensing applications.
- A compact and high-linearity 140-160 GHz active phase shifter in 55 nm BiCMOS(IEEE, 2021-02) Del-Rio-Orduña, D. (David); Sevillano-Calero, F. (Francisco); Berenguer-Pérez, R.J. (Roque José); Gurutzeaga-Zubillaga, I. (Iñaki); Huhtinen, I. (Ismo)This letter presents the design of a 140-160 GHz vector-modulator-type phase shifter, integrated in a 55-nm BiCMOS technology. The circuit is optimized to minimize the occupied area and maximize the linearity, facilitating its integration in D-band phased arrays. Test results show an average insertion loss of 4.5 dB, an OP 1 dB of -3.7 dBm, and rms gain/phase errors lower than 1.4 dB and 7.5 degrees. The circuit core occupies 0.05 mm(2), consuming less than 66 mW of dc power.
- A compact, wideband, and temperature robust 67-90-GHz SiGe power amplifier with 30% PAE(IEEE, 2019-05) Solar-Ruiz, H. (Hector); Del-Rio-Orduña, D. (David); Berenguer-Pérez, R.J. (Roque José); Beriain, A. (Andoni); Gurutzeaga-Zubillaga, I. (Iñaki)This letter presents the design of a compact, wideband, and high-efficiency E-band power amplifier, integrated in a 0.13-mu m BiCMOS process and occupying 0.3 mm(2). It consists of a single-stage balanced amplifier, with HBT transistors in cascode configuration. The power amplifier (PA) is biased in class AB, with a dc consumption of 156 mW. A compact bias circuit is employed to achieve temperature robustness, while the layout is optimized for wideband and highly efficient operation. Measurements show a peak power gain of 15.3 dB at 83 GHz, with a 29.3% fractional bandwidth and less than 1-dB degradation over a 25 degrees C-85 degrees C temperature range. The peak output power at saturation and 1-dB compression is 18.6 and 13.6 dBm, respectively, and the maximum power-added efficiency (PAE) is 30.7%.