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dc.creatorDel-Rio-Orduña, D. (David)-
dc.creatorGurutzeaga-Zubillaga, I. (Iñaki)-
dc.creatorRezola-Garciandia, A. (Ainhoa)-
dc.creatorSevillano Berasategui, J. F. (Juan Francisco)-
dc.creatorVelez-Isasmendi, I. (Igone)-
dc.creatorPuyal, V. (Vincent)-
dc.creatorGonzález-Jiménez, J.L. (José Luís)-
dc.creatorBerenguer-Pérez, R.J. (Roque José)-
dc.date.accessioned2024-01-09T09:49:37Z-
dc.date.available2024-01-09T09:49:37Z-
dc.date.issued2017-05-
dc.identifier.citationDel Rio, D., Gurutzeaga, I., Rezola, A., Sevillano, J. F., Velez, I., Puyal, V., ... & Berenguer, R. (2017). A 15–21 GHz I/Q upconverter with an on-chip linearization circuit for 10 Gbps mm-wave links. IEEE Microwave and Wireless Components Letters, 27(5), 512-514.es_ES
dc.identifier.issn1531-1309-
dc.identifier.urihttps://hdl.handle.net/10171/68215-
dc.description.abstractThis letter presents a 15-21 GHz I/ Q upconverter, based on two Gilbert-cell mixers with an on-chip wideband linearization loop that extends the linear region and allows power efficient operation at backoff power levels. A quadrature LO signal is generated using an integrated two-stage polyphase filter. Measurements show a conversion gain of -5.5 dB, an output 1-dB compression point of 0 dBm, and an image suppression of 40 dB over the 6-GHz output bandwidth. An error vector magnitude of 3.5% is obtained for a 10-Gb/s 64-QAM signal with a bandwidth of 2 GHz. The circuit is integrated in a 55-nm BiCMOS process and occupies 1.07 mm(2) . The dc power consumption is 61 mW.es_ES
dc.language.isoenges_ES
dc.publisherIEEEes_ES
dc.rightsinfo:eu-repo/semantics/closedAccesses_ES
dc.subject64-QAM.es_ES
dc.subjectI/Q modulator.es_ES
dc.subjectK-band.es_ES
dc.subjectMixer.es_ES
dc.subjectRF integrated circuits.es_ES
dc.titleA 15-21 GHz I/Q upconverter with an on-chip linearization circuit for 10 Gbps mm-wave tinks.es_ES
dc.typeinfo:eu-repo/semantics/articlees_ES
dc.identifier.doi10.1109/LMWC.2017.2690868-

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